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Bob Zeidman

Designing with FPGAs and CPLDs

★★★★★
★★★★★
€217.00
A01=Bob Zeidman
A7 Ao
Age Group_Uncategorized
Age Group_Uncategorized
analysis
Application Specific Integrated Circuit
ASIC
ATPG
Author_Bob Zeidman
automatic-update
Category1=Non-Fiction
Category=UMX
chains
Combinatorial Logic
Configurable Logic Blocks
COP=United Kingdom
CPLD
Delivery_Pre-order
devices
eq_computing
eq_isMigrated=2
eq_non-fiction
formal
Formal Verification
FPGA
FPGA Architecture
FPGA Design
FPGA Vendor
Gate Level Description
Hdl Code
IP Core
Language_English
LFSR.
PA=Temporarily unavailable
Power Consumption
Price_€100 and above
programmable
Programmable Devices
PS=Active
Reconfigurable Computing
RTL
scan
Scan Chains
softlaunch
static
Static Timing Analysis
Static Timing Analysis Tools
Switch Matrix
synchronous
Synchronous Design
timing
verification

Product details

  • ISBN 9781138436442
  • Weight: 453g
  • Dimensions: 190 x 240mm
  • Publication Date: 18 Dec 2017
  • Publisher: Taylor & Francis Ltd
  • Publication City/Country: GB
  • Product Form: Hardback
  • Language: English
Delivery/Collection within 10-20 working days

Our Delivery Time Frames Explained
2-4 Working Days: Available in-stock

10-20 Working Days: On Backorder

Will Deliver When Available: On Pre-Order or Reprinting

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Description
Choose the right programmable logic devices and development tools Understand the design, verification, and testing issues Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technolog
About Bob Zeidman
Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI