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Designing Network On-Chip Architectures in the Nanoscale Era

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Bisection Bandwidth
Buffer Slots
Buffered Channels
Cache Blocks
Cache Coherence Protocol
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Category=UYF
chip multiprocessors
Clock Tree
Configuration Bits
End Node
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Execution Time
experimental NoC platform implementation
hardware microarchitecture
Head Flits
IBM Power7
Input Buffer
Input Port
interconnect topology
L2 Cache
multicore processor design
multiprocessor systems
Network Interface
Output Port
parallel computing systems
Power Consumption
Raw Channels
Routing Algorithm
Scratchpad Memory
Superscalar Processors
Switch Fabric
Tile Architecture
Upstream Switch
Virtual Channels

Product details

  • ISBN 9781439837108
  • Weight: 1140g
  • Dimensions: 156 x 234mm
  • Publication Date: 18 Dec 2010
  • Publisher: Taylor & Francis Inc
  • Publication City/Country: US
  • Product Form: Hardback
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Description

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.

Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera’s TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests.

A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs—consistently focusing on topics most pertinent to real-world NoC designers.
About

José Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.