A01=Bob Zeidman
A7 Ao
analysis
Application Specific Integrated Circuit
ASIC
ATPG
Author_Bob Zeidman
Category=UYF
chains
Combinatorial Logic
Configurable Logic Blocks
CPLD
devices
digital circuit synthesis
electronic design automation
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eq_computing
eq_isMigrated=1
eq_isMigrated=2
eq_nobargain
eq_non-fiction
formal
Formal Verification
FPGA
FPGA Architecture
FPGA Design
FPGA Vendor
Gate Level Description
graduate engineering textbook
hardware description languages
Hdl Code
IP Core
LFSR.
logic optimization techniques
Power Consumption
programmable
Programmable Devices
programmable logic device design workflow
Reconfigurable Computing
RTL
scan
Scan Chains
static
Static Timing Analysis
Static Timing Analysis Tools
Switch Matrix
synchronous
Synchronous Design
timing
timing verification methods
verification
Product details
- ISBN 9781578201129
- Weight: 440g
- Dimensions: 191 x 235mm
- Publication Date: 09 Jan 2002
- Publisher: Taylor & Francis Ltd
- Publication City/Country: GB
- Product Form: Paperback
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* Choose the right programmable logic devices and development tools * Understand the design, verification, and testing issues * Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technolog
Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI
