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Digital VLSI Design and Simulation with Verilog

Suman Lata Tripathi | Sobhit Saxena | Sanjeet K. Sinha | Govind S. Patel
€116.99
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A01=Govind S. Patel
A01=Sanjeet K. Sinha
A01=Sobhit Saxena
A01=Suman Lata Tripathi
analog VLSI
Author_Govind S. Patel
Author_Sanjeet K. Sinha
Author_Sobhit Saxena
Author_Suman Lata Tripathi
Behavioral Model
Category=TJ
CMOS design
combinational circuit design
CPLD
dataflow model
digital VLSI
eq_bestseller
eq_isMigrated=1
eq_nobargain
eq_non-fiction
eq_tech-engineering
FPGA
FPGA architecture
gate level model
hardware description language
HDL
Logic Synthesis
NMOS design
PLD
PMOS design
sequential circuit design
SPLD
switch Level Model
User Defined Primitives

Product details

  • ISBN 9781119778042
  • Weight: 454g
  • Dimensions: 10 x 10mm
  • Publication Date: 04 Jan 2022
  • Publisher: John Wiley & Sons Inc
  • Publication City/Country: US
  • Product Form: Hardback
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Description

Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field

Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design.

Through eleven insightful chapters, you�ll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. You�ll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like:

  • A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling
  • A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture
  • An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog
  • A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board

    Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields.

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    About Govind S. Patel | Sanjeet K. Sinha | Sobhit Saxena | Suman Lata Tripathi

    Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India.

    Sobhit Saxena is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from IIT Roorkee, India.

    Sanjeet K. Sinha, PhD, is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India.

    Govind S. Patel, PhD, is Professor of VLSI Design at IIMT College of Engineering, Greater Noida, UP, India. He received his doctorate from Thapar University in Patiala, India.

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