Implementing Parallel and Distributed Systems
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- ISBN 9781032151229
- Weight: 453g
- Dimensions: 178 x 254mm
- Publication Date: 13 Apr 2023
- Publisher: Taylor & Francis Ltd
- Publication City/Country: GB
- Product Form: Paperback
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Parallel and distributed systems (PADS) have evolved from the early days of computational science and supercomputers to a wide range of novel computing paradigms, each of which is exploited to tackle specific problems or application needs, including distributed systems, parallel computing, and cluster computing, generally called high-performance computing (HPC). Grid, Cloud, and Fog computing patterns are the most important of these PADS paradigms, which share common concepts in practice.
Many-core architectures, multi-core cluster-based supercomputers, and Cloud Computing paradigms in this era of exascale computers have tremendously influenced the way computing is applied in science and academia (e.g., scientific computing and large-scale simulations). Implementing Parallel and Distributed Systems presents a PADS infrastructure known as Parvicursor that can facilitate the construction of such scalable and high-performance parallel distributed systems as HPC, Grid, and Cloud Computing.
This book covers parallel programming models, techniques, tools, development frameworks, and advanced concepts of parallel computer systems used in the construction of distributed and HPC systems. It specifies a roadmap for developing high-performance client-server applications for distributed environments and supplies step-by-step procedures for constructing a native and object-oriented C++ platform.
FEATURES:
- Hardware and software perspectives on parallelism
- Parallel programming many-core processors, computer networks and storage systems
- Parvicursor.NET Framework: a partial, native, and cross-platform C++ implementation of the .NET Framework
- xThread: a distributed thread programming model by combining thread-level parallelism and distributed memory programming models
- xDFS: a native cross-platform framework for efficient file transfer
- Parallel programming for HPC systems and supercomputers using message passing interface (MPI)
Focusing on data transmission speed that exploits the computing power of multicore processors and cutting-edge system-on-chip (SoC) architectures, it explains how to implement an energy-efficient infrastructure and examines distributing threads amongst Cloud nodes. Taking a solid approach to design and implementation, this book is a complete reference for designing, implementing, and deploying these very complicated systems.
Alireza Poshtkohi applies computer science and mathematics to tackle grand research challenges in engineering, physics, and medicine. He has worked internationally in both academia and industry in many different roles ranging from computer scientist, neuroscientist, university lecturer, electronics engineer, software engineer, IT consultant and data centre architect, to full-stack developer. He holds BSc and MSc degrees and a PhD in electrical and electronics engineering and computational neuroscience, respectively. To date, he has taught 17 courses—such as parallel algorithms, advanced algorithms, operating systems, and computer networks, to name just a few—in electrical and computer engineering departments at different universities. His current research interests include applied mathematics, biophysics, high-performance computing, and theoretical physics.
M. B. Ghaznavi-Ghoushchi holds a BSc degree from Shiraz University, Shiraz, Iran (1993), and MSc and PhD both from Tarbiat Modares University (TMU), Tehran, Iran, in 1997 and 2003, respectively. During 2003–2004, he was a researcher at TMU Institute of Information Technology. He is the founder and director of High-Performance and Cloud Computing (HPCC) and Integrated Circuits and Systems (ICS) laboratories at Shahed University. He is currently an associate professor at Shahed University, Tehran, Iran. His interests include VLSI Design; Low Power and Energy-Efficient circuits and systems; Computer-Aided Design Automation for Mixed Signal; and UML-based designs for SoC and Mixed-Signal.
