Logic-timing Simulation And The Degradation Delay Model
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€102.99
A01=Jorge Juan Chico
A01=Manuel Jesus Bellido Diaz
A01=Manuel Valencia
Author_Jorge Juan Chico
Author_Manuel Jesus Bellido Diaz
Author_Manuel Valencia
Category=UGK
CMOS
Degradation Effect
Delay Modeling
Digital Integrated Circuits
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Logic-Timing Simulation
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Product details
- ISBN 9781860945892
- Publication Date: 30 Nov 2005
- Publisher: Imperial College Press
- Publication City/Country: GB
- Product Form: Hardback
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This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)
