Multicore Technology

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Architecture and Design Flow
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B01=Muhammad Yasir Qadri
B01=Stephen J. Sangwine
Buffer Length
Cache Coherence
Cache Line
cache management strategies
Cache Miss
Cache Miss Rates
Category1=Non-Fiction
Category=THR
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Category=TQ
Category=UB
Category=UKP
Category=UY
Category=UYF
COP=United States
Critical Section
Debugging
Debugging Methods
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DMA Channel
Dram Access
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eq_computing
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ESX Server
Execution Control
Execution Time
IP Core
L1 Cache
Language_English
Memory Systems
Model Based Design Approach
multicore processor design techniques
Multithreaded Software
Networks-on-Chip
networks-on-chip optimization
NoC Architecture
NoC Design
Occupancy Points
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parallel computing systems
Parallelism and Optimization
Power Consumption
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Routing Algorithm
softlaunch
Software Debugging
system-on-chip design
thread scheduling algorithms
TM
Trace Generation
transactional memory models
Virtual Channels

Product details

  • ISBN 9781439880630
  • Weight: 850g
  • Dimensions: 156 x 234mm
  • Publication Date: 26 Jul 2013
  • Publisher: Taylor & Francis Inc
  • Publication City/Country: US
  • Product Form: Hardback
  • Language: English
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The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing.

The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.

Muhammad Yasir Qadri, Stephen J. Sangwine