Speculative Execution in High Performance Computer Architectures

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Address Prediction
advanced compiler strategies
branch
Branch Prediction
Branch Predictor
cache
Cache Line
Cache Misses
Category=UYF
compiler
computer architecture research
Conditional Branch
data
Data Dependence
Data Prefetching
Data Speculation
dependence
Dynamic Instructions
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Execution Time
Input Operands
instruction
Instruction Cache
Instruction Fetch
L2 Cache
latency hiding techniques
Linked Data Structures
Load Instructions
memory coherence protocols
Memory Dependence
miss
multithreaded microarchitectures
Naive Speculation
optimization
parallelism
Path Id
prediction
Prefetch Instructions
profile guided optimisation
Speculative Execution
speculative execution methods in processors
Target Addresses
Thread Level Parallelism
Trace Caches

Product details

  • ISBN 9781584884477
  • Weight: 771g
  • Dimensions: 156 x 234mm
  • Publication Date: 26 May 2005
  • Publisher: Taylor & Francis Inc
  • Publication City/Country: US
  • Product Form: Hardback
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Until now, there were few textbooks that focused on the dynamic subject of speculative execution, a topic that is crucial to the development of high performance computer architectures. Speculative Execution in High Performance Computer Architectures describes many recent advances in speculative execution techniques. It covers cutting-edge research projects, as well as numerous commercial implementations that demonstrate the value of this latency-hiding technique. The book begins with a review of control speculation techniques that use instruction cache prefetching, branch prediction and predication, and multi-path execution. It then examines dataflow speculation techniques including data cache prefetching, address value and data value speculation, pre-computation, and coherence speculation. This textbook also explores multithreaded approaches, emphasizing profile-guided speculation, speculative microarchitectures, and compiler techniques.