Digital Signal Processing with Field Programmable Gate Arrays
English
By (author): Uwe Meyer-Baese
- Over 10 new system level case studies designed in VHDL and Verilog
- A new chapter on image and video processing
- An Altera Quartus update and new Model Sim simulations
- Xilinx Atlys board and ISIM simulation support
- Signed fixed point and floating point IEEE library examples
- An overview on parallel all-pass IIR filter design
- ICA and PCA system level designs
- Speech and audio coding for MP3 and ADPCM